First of all thanks for that very cool piece of test gear the QA403 is, very happy with it!
I have been capturing some I2S data from the QA403 front panel expansion connector during a MCU Project I am doing. Something I noticed which took me a bit of time to make out, just wanted to give a feedback and throw that information out there:
The output Level is shown as dBV=dBFS RMS on the Generator, however you can increase that up to 0dBFS without digital clip warning. -3dBFS is 0dBFS peak, so it should clip there already?
…What really happens is that from -3dBFS to 0dBFS the i2s level will stay the same, so there will be no increase in level. Then it goes into clipping from 0dBFS/dBV upwards.
I know this is a small thing but maybe in future versions of the SW there could be a dBFS display next to the dBV value once I2S is engaged or some indication that there is a mismatch between the values at some point?
Another thing I would like to bring up is that the DAC and ADC Pin designations are swapped in the wiki/manual.
(Maybe someone else noticed it already, I didnt find any posts).
The Bit stream is on the ADC pin. In the wiki you can also see the reversed direction of the Buffer/Levelshifter channel.
Hi @Hameg, I think the entire generator section needs a UI overhaul and it will come in time.
I just checked with a scope that the pin shown below was wiggling when I2S was enabled. So unless you are seeing an old picture someplace else, the I2S section on the Wiki is correct. Can you please confirm?
If you specify 0 dBV that will map to a sine that is +/- 1.0 at the tips (0 dBFS). As you push beyond 0 dBV, the sine will start to look like a trapezoid, because the sine that is generated is always clipped to +/- 1.0. If you specify a 16 dBV sine, what leaves the I2S pin will be very close to a square wave +/- 1.0 in amplitude.
When I2S is enabled, if you exceed 0 dBV, you will get an annunciator telling you the digital output is clipping.
Concerning pinout:
Ohhh okay that was my bad, seems like I was referring to the QA402… sorry about that!
I did not catch that the pins were swapped between versions…
Concerning gen level:
I will refer to the dBV gen setting as “dBFS” setting for this post
What I wanted to bring up is that for -3dBFS to 0dBFS (rms) level setting, I2S Generator level does not change (which is not indicated anywhere). It does not clip either. Just stays at 0dBFS(peak).
Its a very minute detail but made me search for a bug in my MCU code (which does dBFS level calculations ). This was because I thought it was calculating the levels wrong, since the number on the QA40x UI was not matching the level my MCU calculated. But only from -3dBFS to 0dBFS. Then I went to capture the data with my logic analyzer (…dumping the data to csv and then plotting it) and the signal was not clipping, but also did not change in level for the level settings -3dFS to 0dBFS. Its a small detail, not a “malfunction” necessarily.
Just wanted to bring this up because I stumbled upon it. I expected something to happen on the I2S signal when increasing the level from -3dBFS to 0dBFS but it did not, the UI did not reflect that.
